ARM has rolled out a successor to its popular but aging ARM7TDMI processor core. CPU product manager Richard York describes the new Cortex-R4 as a midrange microprocessor that fills the gap between the M3 at the low end, and the high-performance A8 and ARM 1156. Those products all leverage the firm’s 16/32-bit Thumb-2 instruction set, so ARM7 applications should work on the R4, only better, because the new chip is said to be four to five times faster than the ARM7 (200-250MHz versus 40-50MHz), and offer double the instruction execution efficiency. Size-wise, the new chip contains about triple the number of gates in the ARM7, but York figures that with advanced processes it shouldn’t require much more silicon, and even if it did, the performance gain would justify the extra cost.

The efficiency gain comes from features like a vectored interrupt controller (VIC) port that saves clock cycles by doing in hardware what the ARM7 does in software. The VIC works in concert with a pre-fetch and branch prediction unit to keep the processor continually fed with data. The R4 can be configured with up to 64KB of instruction cache and 64Kb of data cache (versus 0KB of data cache in the ARM7).

The R4 also includes an OSEK-compliant memory protection unit; a tightly coupled memory (TCM) arbiter and interface for 2-cycle local memory access with ECC support; a 64-bit AMBA 3 AXI master interface, and a 64-bit AMBA 3 AXI slave interface, the latter including a DMA port. For developers, ARM’s new microprocessor offers CoreSight debug and embedded trace macrocell (ETM) ports.

York obviously hopes that customers will use the R4 to take applications to the next level. He suggested, for example, that a customer using the ARM7 core in an ABS application might consider the R4 for ESP chassis control.

Texas Instruments, which uses the ARM7 in its TMS470 microcontroller family, is evaluating the R4 but has not yet committed to it. Competitors/customers Freescale (PowerPC), Renesas Technology (SH-4) and NEC Electronics America V850 were unavailable for comment.